1. Field of the Invention
The present invention relates to a split gate type flash memory. More particularly, the present invention relates to a split gate type flash memory having the shape of an active region that improves an endurance characteristic as well as program/erase efficiency.
2. Description of the Related Art
As shown in FIG. 1, a split gate type flash memory has a structure wherein a floating gate 22 and a control gate 29 are separated from each other. The floating gate 22 is electrically insulated from the outside. Adjacent the floating gate 22 is an intergate insulating layer 25 and a gate insulating layer 20. Information is stored in a memory cell by using the properties that current in a memory cell changes depending on electron injection (program)/electron discharge (erase) into/from the floating gate 22. Electron injection of hot electrons in a channel 18 into the floating gate 22 is performed by a channel hot electron injection (CHEI) mechanism. Electron discharge is carried out by Fowler-Nordheim (F-N) tunneling through a tunnel insulating layer 24 between the floating gate 22 and the control gate 29. In connection with the electron injection (program) and electron discharge (erase), a voltage distribution is explained in an equivalent capacitor model shown in FIG. 2.
In the electron injection (program) operation, a voltage Vwl is applied to the control gate 29 such that, when the voltage of a source 14 is about Vs=11 V and the voltage of a drain 16 is about Vbl=0 V, the channel 18 opens slightly. In this case, a voltage corresponding to about Vs//Cs/Ctot is applied to the floating gate 22, where Cs, Ctun, and Cgox denote capacitances and Cs+Ctun+Cgox=Ctot. Accordingly, Cs/Ctot is an important factor for determining the efficiency of a cell. Since the voltage Vf which is applied to the floating gate 22 generates a vertical field by which hot electrons are injected into the floating gate 22, the value of this voltage must be increased in order to increase electron injection (program) efficiency.
In the electron discharge (erase) operation, F-N tunneling through the tunnel insulating layer 24 made of an interpoly oxide is used. In this case, voltages of Vs=0 V and Vwl=15 V are applied. Here, the voltage of the floating gate 22 is proportional to (Ctotxe2x88x92Csxe2x88x92Cgox)/Ctot. Thus, in order to increase an effective voltage (Vwlxe2x88x92Vf), Cs has to be increased, and Ctun has to be reduced. An effective voltage in the electron discharge operation significantly affects the endurance characteristic of a cell as well as the electron discharge (erase) efficiency. In the F-N tunneling mechanism through the tunnel insulating layer 24 made of an interpoly oxide, a reduction in tunnel current caused by electron traps in an insulating layer is known to be a major cause of degradation. This degradation can be suppressed by an increase in effective voltage. Accordingly, if materials of an insulating layer are the same, each capacitance depends on a cell structure, in particular the thickness and area of the insulating layer. On-going efforts are being made in order to overcome this drawback.
As shown in FIG. 3, a conventional split gate cell has a structure in which the width of an active region is uniform like in the existing metal oxide semiconductor field effect transistor (MOSFET). The capacitance Cs affects the area A, which is formed by expanding the source 14 so that it is overlapped by the floating gate 22, and the thickness of a gate insulating layer 20 (not shown). There is, however, a limitation in reducing the thickness of the gate insulating layer and increasing the expansion length of the source 14. As a result, the conventional split gate cell has a disadvantage in that it is difficult to increase the capacitance Cs. Additionally depicted in FIG. 3 are a control gate 29, a channel 18, and a drain 16.
FIG. 4 indicates that during an electron discharge operation of a split gate type flash memory the current Ids is reduced by electron traps as the number of electron injection/discharge cycles, i.e., the number of program/erase cycles is increased. Such an endurance failure in a split gate type memory cell is known to result from a reduction in tunneling current during electron discharge. However, it is impossible to completely remove this phenomenon because the phenomenon is intrinsic due to electron traps formed by an interpoly tunnel insulating layer being of poor quality and thick compared with the gate insulating layer. Accordingly, a cell having a structure addressing this point needs to be adopted.
To solve at least the above problem, it is a feature of at least one embodiment of the present invention to provide a split gate type flash memory having an active region which increases, and thereby improves, the program/erase efficiency and the endurance characteristic.
Another feature of at least one embodiment of the present invention provides a split gate type flash memory including a substrate; a source, a drain and a channel provided over the substrate; a gate insulating layer provided on the source, the drain and the channel; a floating gate stacked on the gate insulating layer overlying the source and channel; an intergate insulating layer and a tunnel insulating layer stacked on the top and the side of the floating gate, respectively; and a control gate stacked on the intergate insulating layer, the tunnel insulating layer, and the gate insulating layer. In this split gate type flash memory, an active region is formed so that the channel width under the floating gate is larger than the channel width under the control gate.
Another feature of an embodiment of the present invention provides a split gate type flash memory including a substrate; a source, a drain and a channel provided over the substrate; a gate insulating layer provided on the source, the drain and the channel; a floating gate stacked on the gate insulating layer overlying the source and channel; an intergate insulating layer and a tunnel insulating layer stacked on the top and the side of the floating gate, respectively; and a control gate stacked on the intergate insulating layer, the tunnel insulating layer and the gate insulating layer. In this split gate type flash memory, an active region is formed so that the source underlying the floating gate is larger than the width of the channel under the control gate.
Yet another feature of an embodiment of the present invention provides a split gate type flash memory including a substrate; a source, a drain and a channel provided over the substrate; a gate insulating layer provided on the source, the drain and the channel; a floating gate stacked on the gate insulating layer overlying the source and channel; an intergate insulating layer and a tunnel insulating layer stacked on the top and the side of the floating gate, respectively; and a control gate stacked on the intergate insulating layer, the tunnel insulating layer and the gate insulating layer. Furthermore, in this split gate type flash memory, an active region is formed so that the width of the channel under the floating gate is larger than the width of the channel under the control gate, and the source underlying the floating gate is larger than the width of the channel under the control gate.
These and other features of the embodiments of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description of the preferred embodiments that follows.